1. Field of the Invention
The present invention relates to the field of data transfer. More specifically, the present invention relates to an asynchronous interface enabling both a physically distributed, synchronous communications network and processor nodes, coupled to the communications network, to operate at their maximum clocking frequencies.
2. Background Art Related to the Invention
In recent years, the computer industry has begun to fully appreciate substantial performance advantages in transferring information (i.e., data, addresses and control information) between processor nodes. A "processor node" is generally defined as an apparatus comprising a central processing unit ("CPU"), associated memory and interface circuitry. These processor nodes typically are coupled separately or collectively to a conventional interconnect component which, in turn, is coupled to a synchronous communications network i.e., a physically distributed medium being clocked at a predetermined network clocking frequency.
Traditionally, for the synchronous communications network to operate properly, each processor node, coupled to the network through conventional interconnect components, is required to operate at the network clocking frequency. This requirement places burdensome restrictions on the overall performance and architecture of the communications network. Due to continual advancements in multi-processing technologies and broader usage of synchronous communications networks for high-speed parallel-processing applications i.e. supercomputers, a number of performance-related disadvantages have emerged. One such disadvantage is that processor nodes, which may operate at a maximum clocking frequency greater than the network clocking frequency, would now be required to operate at the network clocking frequency. As a result, the advanced processor nodes would not achieve optimal performance.
Another disadvantage relates to difficulties in upgrading the supercomputer. One reason for such difficulty is caused by the conventional interconnect components. More specifically, the conventional interconnect components usually are coupled to a back-plane of the supercomputer. Thus, in order to upgrade the network of the supercomputer, for example enhancing its clocking frequency to accommodate advanced processor nodes, the back-plane of the supercomputer must be replaced which is extremely labor intensive. Rather, businesses usually replace the entire supercomputer.
Another basis for such difficulty occurs because the performance of the synchronous communications network of the supercomputer generally is based on the slowest processor node. As processor nodes become more advanced and operate at higher clocking frequencies, it is becoming difficult to substitute these advanced processor nodes for prior processor nodes without a complete reconfiguration of the communications network in order to maintain existing data and clock phase relationships. It is contemplated that even if the advanced processor node is adapted to the communications network, it may have no appreciable effect on the overall performance of the supercomputer provided there exists a slower processor node. This disadvantage also exists in connection with adapting customized processor nodes and standard processor nodes to the same synchronous communications network. Since customized processor nodes usually operate at unique operating frequencies, they also are difficult to implement on the synchronous communications network, and if adaptable, may require limiting the clocking frequency (and performance) of either the custom processor node, the standard processor node or both types of processor nodes through pseudo-asynchronous interfaces.
In order to mitigate these above-identified disadvantages, "pseudo-asynchronous" interfaces are being employed between the synchronous communications network of the supercomputer and each parallel processor node. A "pseudo-asynchronous" is generally a combination of discrete logic devices which adds unnecessary latency through redundant buffering in order to augment or limit its network clocking frequency by "m/n", where "m" and "n" are arbitrary integers. Thus, the pseudo-asynchronous interface is not truly asynchronous because it has a known relationship with the network clocking frequency so that it inherently possesses the same problems in maintaining a clock phase relative to data as any synchronous communications network with nodes that are physically and electrically separated by a large distance.
Therefore, in light of the foregoing, it is appreciated that there exists a need for reducing or eliminating the disadvantages associated with conventional physically distributed, synchronous communications network employing multiple processor nodes operating at identical or different operating frequencies. Hence, it is an object of the invention to provide an asynchronous interface which allows each processor node to operate at its maximum clocking frequency instead of at a clocking frequency which conforms to the other processor nodes and the communications network.
It is further an object of the present invention to provide an apparatus and method which enables the synchronous communications network to operate at its maximum bandwidth without consideration of the processor node clocking frequency.
It is still another object of the present invention to provide an asynchronous interface embedded inside a routing component to simplify the clocking scheme for the network in precluding distribution of the clock.
It is another object of the present invention to provide an apparatus which support incremental upgrades of a processor node without altering the network clocking frequency.